div.vhd

是vhdl语言

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity div is

port(clkin :in std_logic;
     
     clkout : out std_logic
    
);
end div;

architecture div_arc of div is
signal count: std_logic_vector (32 downto 0);
--signal full : std_logic;
begin
	--clkout<=full;
	process(clkin)
	begin
		if (clkin'event and clkin='1') then
			if (count=100000000) then
				count<="000000000000000000000000000000000";
				clkout<='0';
			else 
				count<=count+1;
                if (count=50000000) then
					clkout<='1';
				end if;
			end if;
		end if;
	end process;
end div_arc;
				
			--if (count=100000000) then
			--count<="000000000000000000000000000000000";
			--full<=not full;
			--else	count<=count+1;
		    --end if;
		--end if;
	--end process;
	--clkout<=full;
--end div_arc;