📄 hbf_da_timeshare.mdl
字号:
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input3"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input4"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 267, 160, 283]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input4"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input5"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 297, 160, 313]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input5"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input6"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 327, 160, 343]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input6"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input7"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 357, 160, 373]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input7"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input8"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 387, 160, 403]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input8"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input9"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [95, 417, 160, 433]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input9"
nSgCpl "0"
}
Block {
BlockType Reference
Name "NOT"
Ports [1, 1]
Position [1135, 492, 1175, 508]
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "NOT1"
Ports [1, 1]
Position [535, 92, 560, 108]
SourceBlock "gate_alteradspbuilder/NOT"
SourceType "LogiBit AlteraBlockSet"
Operator "NOT"
Inputs "2"
}
Block {
BlockType Reference
Name "Output"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [1405, 497, 1470, 513]
SourceBlock "bus_alteradspbuilder/Output"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Output Port"
bwl "38"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Output"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Parallel \nAdder Subtractor"
Ports [10, 1]
Position [915, 322, 970, 518]
SourceBlock "arithm_alteradspbuilder/Parallel \nAdde"
"r Subtractor"
SourceType "Sum AlteraBlockSet"
Inputs "10"
direction "++++++++++"
pipeline on
clken off
MaskValue "1"
}
Block {
BlockType Reference
Name "Pipelined Adder"
Ports [6, 2]
Position [1270, 407, 1355, 533]
SourceBlock "arithm_alteradspbuilder/Pipelined Adder"
SourceType "HDLEntity AlteraBlockSet"
BusType "Signed Integer"
bwl "38"
bwr "0"
pipeline "1"
AddSubDirection "ADD"
UseControlInputs on
HDLInputPortsMappingAltera "dataa.38.0.s,datab.38.0.s,cin.1.0.b,"
"add_sub.1.0.b,clken.1.0.b"
HDLOutputPortsMappingAltera "cout.1.0.b,result.38.0.s"
HDLImplicitPortsMappingAltera "clock.clock, 6.sclror"
HDLParameterMappingAltera "width.38.positive,pipeline.1.natural,"
"IsUnsigned.0.natural"
HDLLibraryInformationAltera "library dspbuilder;use dspbuilder.d"
"spbuilderblock.all;"
HDLComponentNameAltera "sLpmAddSub"
}
Block {
BlockType SubSystem
Name "SoftMult_M4K"
Ports [11, 10]
Position [580, 75, 780, 775]
ForegroundColor "blue"
AncestorBlock "ALTELINK/AltLab/HDL SubSystem"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
MaskType "SubSystem AlteraBlockSet"
MaskSelfModifiable on
MaskIconFrame on
MaskIconOpaque on
MaskIconRotate "none"
MaskIconUnits "autoscale"
System {
Name "SoftMult_M4K"
Location [-61, 99, 1146, 1025]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "107"
Block {
BlockType Inport
Name "coef_sel_bit]"
Position [30, 58, 60, 72]
ForegroundColor "blue"
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_1[17:0]"
Position [30, 88, 60, 102]
ForegroundColor "blue"
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_2[17:0]"
Position [30, 173, 60, 187]
ForegroundColor "blue"
Port "3"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_3[17:0]"
Position [30, 258, 60, 272]
ForegroundColor "blue"
Port "4"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_4[17:0]"
Position [25, 338, 55, 352]
ForegroundColor "blue"
Port "5"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_5[17:0]"
Position [25, 418, 55, 432]
ForegroundColor "blue"
Port "6"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_6[17:0]"
Position [25, 503, 55, 517]
ForegroundColor "blue"
Port "7"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_7[17:0]"
Position [30, 583, 60, 597]
ForegroundColor "blue"
Port "8"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_8[17:0]"
Position [30, 668, 60, 682]
ForegroundColor "blue"
Port "9"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_9[17:0]"
Position [35, 748, 65, 762]
ForegroundColor "blue"
Port "10"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "data_10[17:0]"
Position [35, 828, 65, 842]
ForegroundColor "blue"
Port "11"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Input"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [85, 87, 150, 103]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input"
ppat "C:\\Data\\IP\\FIR\\Samsung\\Coef_he"
"x\\DSPBuilder_test"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input1"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [85, 172, 150, 188]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input1"
ppat "C:\\Data\\IP\\FIR\\Samsung\\Coef_he"
"x\\DSPBuilder_test"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input2"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [85, 257, 150, 273]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input2"
ppat "C:\\Data\\IP\\FIR\\Samsung\\Coef_he"
"x\\DSPBuilder_test"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input3"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [80, 337, 145, 353]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input3"
ppat "C:\\Data\\IP\\FIR\\Samsung\\Coef_he"
"x\\DSPBuilder_test"
nSgCpl "0"
}
Block {
BlockType Reference
Name "Input4"
Description "Sign Binary Fractionnal"
Ports [1, 1]
Position [80, 417, 145, 433]
SourceBlock "bus_alteradspbuilder/Input"
SourceType "AltBus AlteraBlockSet"
sgn "Signed Integer"
nodetype "Input Port"
bwl "18"
bwr "0"
sat off
rnd off
bp off
mask_cst "0"
LocPin "any"
cst "0"
modulename "Input4"
ppat "C:\\Data\\IP\\FIR\\Samsung\\Coef_he"
"x\\DSPBuilder_test"
nSgCpl "0"
}
Block {
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -