fifo2.syr

使用VHDL编程的异步FIFO程序 经调试可运行

*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <fifo2> ...

Optimizing unit <async_cmp> ...
Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register rptr_empty2_rbin_3 equivalent to rptr_empty2_rptr_3 has been removed
Register wptr_full2_wbin_3 equivalent to wptr_full2_wptr_3 has been removed
Found area constraint ratio of 100 (+ 5) on block fifo2, actual ratio is 1.
FlipFlop wptr_full2_wptr_1 has been replicated 1 time(s)
FlipFlop wptr_full2_wptr_3 has been replicated 1 time(s)
FlipFlop wptr_full2_wptr_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fifo2.ngr
Top Level Output File Name         : fifo2
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Macro Statistics :
# RAM                              : 1
#      16x8-bit dual-port distributed RAM: 1
# Registers                        : 8
#      1-bit register              : 4
#      4-bit register              : 4
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2
# Comparators                      : 1
#      4-bit comparator equal      : 1

Cell Usage :
# BELS                             : 29
#      LUT1                        : 2
#      LUT2                        : 1
#      LUT2_L                      : 2
#      LUT3                        : 3
#      LUT3_D                      : 1
#      LUT3_L                      : 9
#      LUT4                        : 4
#      LUT4_D                      : 4
#      LUT4_L                      : 3
# FlipFlops/Latches                : 21
#      FDC                         : 17
#      FDCP                        : 2
#      FDP                         : 2
# RAMS                             : 8
#      RAM16X1D                    : 8
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 22
#      IBUF                        : 12
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                      28  out of   1920     1%  
 Number of Slice Flip Flops:            21  out of   3840     0%  
 Number of 4 input LUTs:                37  out of   3840     0%  
 Number of bonded IOBs:                 22  out of    141    15%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
wclk                               | BUFGP                  | 20    |
rclk                               | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.516ns (Maximum Frequency: 221.435MHz)
   Minimum input arrival time before clock: 4.987ns
   Maximum output required time after clock: 7.886ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'rclk'
Delay:               4.516ns (Levels of Logic = 3)
  Source:            rptr_empty2_rptr_3 (FF)
  Destination:       rptr_empty2_rempty2 (FF)
  Source Clock:      rclk rising
  Destination Clock: rclk rising

  Data Path: rptr_empty2_rptr_3 to rptr_empty2_rempty2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   0.619   0.895  rptr_empty2_rptr_3 (rptr_empty2_rptr_3)
     LUT2:I0->O            1   0.720   0.240  rptr_empty2__AUX_1<0>46 (CHOICE244)
     LUT4_L:I0->LO         1   0.720   0.100  rptr_empty2__AUX_1<0>59 (CHOICE249)
     LUT3_D:I0->LO         2   0.720   0.000  rptr_empty2__AUX_1<0>76 (N3333)
     FDP:D                     0.502          rptr_empty2_rempty2
    ----------------------------------------
    Total                      4.516ns (3.281ns logic, 1.235ns route)
                                       (72.7% logic, 27.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'wclk'
Delay:               3.907ns (Levels of Logic = 2)
  Source:            wptr_full2_wfull (FF)
  Destination:       wptr_full2_wptr_2_1 (FF)
  Source Clock:      wclk rising
  Destination Clock: wclk rising

  Data Path: wptr_full2_wfull to wptr_full2_wptr_2_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCP:C->Q             5   0.619   0.658  wptr_full2_wfull (wptr_full2_wfull)
     LUT4_D:I3->O          6   0.720   0.688  Ker12361 (N1238)
     LUT3_L:I0->LO         1   0.720   0.000  wptr_full2_Mxor__n0003_Result1 (wptr_full2_wgnext<2>)
     FDC:D                     0.502          wptr_full2_wptr_2
    ----------------------------------------
    Total                      3.907ns (2.561ns logic, 1.346ns route)
                                       (65.5% logic, 34.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'wclk'
Offset:              4.987ns (Levels of Logic = 3)
  Source:            winc (PAD)
  Destination:       wptr_full2_wptr_2_1 (FF)
  Destination Clock: wclk rising

  Data Path: winc to wptr_full2_wptr_2_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   1.492   0.865  winc_IBUF (winc_IBUF)
     LUT4_D:I2->O          6   0.720   0.688  Ker12361 (N1238)
     LUT3_L:I0->LO         1   0.720   0.000  wptr_full2_Mxor__n0003_Result1 (wptr_full2_wgnext<2>)
     FDC:D                     0.502          wptr_full2_wptr_2
    ----------------------------------------
    Total                      4.987ns (3.434ns logic, 1.553ns route)
                                       (68.9% logic, 31.1% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'rclk'
Offset:              4.640ns (Levels of Logic = 3)
  Source:            rinc (PAD)
  Destination:       rptr_empty2_rbin_2 (FF)
  Destination Clock: rclk rising

  Data Path: rinc to rptr_empty2_rbin_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   1.492   0.629  rinc_IBUF (rinc_IBUF)
     LUT4_D:I2->O          3   0.720   0.577  Ker12401 (N1242)
     LUT3_L:I0->LO         1   0.720   0.000  rptr_empty2_Mxor__n0003_Result1 (rptr_empty2_rgnext<2>)
     FDC:D                     0.502          rptr_empty2_rptr_2
    ----------------------------------------
    Total                      4.640ns (3.434ns logic, 1.206ns route)
                                       (74.0% logic, 26.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'rclk'
Offset:              7.886ns (Levels of Logic = 2)
  Source:            rptr_empty2_rptr_3 (FF)
  Destination:       rdata<7> (PAD)
  Source Clock:      rclk rising

  Data Path: rptr_empty2_rptr_3 to rdata<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             13   0.619   0.895  rptr_empty2_rptr_3 (rptr_empty2_rptr_3)
     RAM16X1D:DPRA3->DPO    1   0.720   0.240  fifomem2_Mram_MEM_inst_ramx_1 (rdata_1_OBUF)
     OBUF:I->O                 5.412          rdata_1_OBUF (rdata<1>)
    ----------------------------------------
    Total                      7.886ns (6.751ns logic, 1.135ns route)
                                       (85.6% logic, 14.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'wclk'
Offset:              7.615ns (Levels of Logic = 1)
  Source:            fifomem2_Mram_MEM_inst_ramx_7 (RAM)
  Destination:       rdata<7> (PAD)
  Source Clock:      wclk rising

  Data Path: fifomem2_Mram_MEM_inst_ramx_7 to rdata<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAM16X1D:WCLK->DPO    1   1.963   0.240  fifomem2_Mram_MEM_inst_ramx_7 (rdata_7_OBUF)
     OBUF:I->O                 5.412          rdata_7_OBUF (rdata<7>)
    ----------------------------------------
    Total                      7.615ns (7.375ns logic, 0.240ns route)
                                       (96.8% logic, 3.2% route)

=========================================================================
CPU : 1.80 / 2.03 s | Elapsed : 2.00 / 2.00 s
 
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Total memory usage is 67064 kilobytes