fifo2.syr

使用VHDL编程的异步FIFO程序 经调试可运行

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: fifo2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : fifo2.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : fifo2
Output Format                      : NGC
Target Device                      : xc3s200-4-pq208

---- Source Options
Top Module Name                    : fifo2
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : fifo2.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "async_cmp.v"
Module <async_cmp> compiled
Compiling source file "fifomem2.v"
Compiling source file "rptr_empty2.v"
Module <fifomem2> compiled
Module <rptr_empty2> compiled
Compiling source file "wptr_full2.v"
Module <wptr_full2> compiled
Compiling source file "fifo2.v"
Module <fifo2> compiled
No errors in compilation
Analysis of file <fifo2.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <fifo2>.
Module <fifo2> is correct for synthesis.
 
Analyzing module <async_cmp>.
Module <async_cmp> is correct for synthesis.
 
Analyzing module <fifomem2>.
Module <fifomem2> is correct for synthesis.
 
Analyzing module <rptr_empty2>.
Module <rptr_empty2> is correct for synthesis.
 
Analyzing module <wptr_full2>.
Module <wptr_full2> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <wptr_full2>.
    Related source file is wptr_full2.v.
    Found 4-bit register for signal <wptr>.
    Found 1-bit register for signal <wfull>.
    Found 4-bit adder for signal <$n0002> created at line 25.
    Found 1-bit xor2 for signal <$n0003> created at line 26.
    Found 1-bit xor2 for signal <$n0004> created at line 26.
    Found 1-bit xor2 for signal <$n0005> created at line 26.
    Found 4-bit register for signal <wbin>.
    Found 1-bit register for signal <wfull2>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Multiplexer(s).
Unit <wptr_full2> synthesized.


Synthesizing Unit <rptr_empty2>.
    Related source file is rptr_empty2.v.
    Found 1-bit register for signal <rempty>.
    Found 4-bit register for signal <rptr>.
    Found 4-bit adder for signal <$n0002> created at line 25.
    Found 1-bit xor2 for signal <$n0003> created at line 26.
    Found 1-bit xor2 for signal <$n0004> created at line 26.
    Found 1-bit xor2 for signal <$n0005> created at line 26.
    Found 4-bit register for signal <rbin>.
    Found 1-bit register for signal <rempty2>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred   4 Multiplexer(s).
Unit <rptr_empty2> synthesized.


Synthesizing Unit <fifomem2>.
    Related source file is fifomem2.v.
    Found 16x8-bit dual-port distributed RAM for signal <MEM>.
    -----------------------------------------------------------------------
    | aspect ratio       | 16-word x 8-bit                     |          |
    | clock              | connected to signal <wclk>          | rise     |
    | write enable       | connected to signal <wclken>        | high     |
    | address            | connected to signal <waddr>         |          |
    | dual address       | connected to signal <raddr>         |          |
    | data in            | connected to signal <wdata>         |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <rdata>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronousely. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Summary:
	inferred   1 RAM(s).
Unit <fifomem2> synthesized.


Synthesizing Unit <async_cmp>.
    Related source file is async_cmp.v.
    Found 4-bit comparator equal for signal <$n0003> created at line 20.
    Found 1-bit xor2 for signal <$n0011> created at line 10.
    Found 1-bit xor2 for signal <$n0012> created at line 10.
    Summary:
	inferred   1 Comparator(s).
Unit <async_cmp> synthesized.


Synthesizing Unit <fifo2>.
    Related source file is fifo2.v.
WARNING:Xst:1780 - Signal <raddr> is never used or assigned.
WARNING:Xst:1780 - Signal <waddr> is never used or assigned.
Unit <fifo2> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                             : 1
  16x8-bit dual-port distributed RAM: 1
# Registers                        : 8
  4-bit register                   : 4
  1-bit register                   : 4
# Multiplexers                     : 2
  2-to-1 multiplexer               : 2
# Adders/Subtractors               : 2
  4-bit adder                      : 2
# Comparators                      : 1
  4-bit comparator equal           : 1
# Xors                             : 8
  1-bit xor2                       : 8

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================