pack_pro.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 52 行

--************************************
--*  PACKAGE PROCEDURE DECLARATION   *
--************************************

library IEEE;
use IEEE.std_logic_1164.all;

PACKAGE PACK_PRO IS

procedure DEMUL4 (
                  signal D: in std_logic;
                  signal S: in std_logic_vector(1 downto 0);
                  signal Y: out std_logic_vector(0 to 3)
                 );
procedure DEMUL2 (
                  signal D: in std_logic;
                  signal S: in std_logic;
                  signal Y: out std_logic_vector(0 to 1)
                 );
end PACK_PRO;
            
PACKAGE BODY PACK_PRO IS
                        
procedure DEMUL4 (
                  signal D: in std_logic;
                  signal S: in std_logic_vector(1 downto 0);
                  signal Y: out std_logic_vector(0 to 3)
                 ) is
begin
    case S is
         when "00"   => Y <= D & "111";
         when "01"   => Y <= '1' & D & "11";
         when "10"   => Y <= "11" & D & '1';
         when others => Y <= "111" & D;
    end case; 
end DEMUL4;

procedure DEMUL2 (
                  signal D: in std_logic;
                  signal S: in std_logic;
                  signal Y: out std_logic_vector(0 to 1)
                 ) is  
begin
    case S is
         when '0'    => Y <= D & '1';
         when others => Y <= '1' & D;
    end case;
end DEMUL2;
                              
end PACK_PRO;