dem_pack.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 29 行

--*****************************************
--*   1 To 8 Demulptilexer (PROCEDURE)    *
--*  One 1 To 4 DEMUL Three 1 To 2 DEMUL  *
--*      Those Declare In PACK_PRO        *
--*         Filename : DEM_PACK           *
--*****************************************

library IEEE;
use IEEE.std_logic_1164.all;
use work.pack_pro.all;

entity DEM_PACK is
    port (
          DIN :in STD_LOGIC;
          S   :in STD_LOGIC_VECTOR (2 downto 0);
          Y   :out STD_LOGIC_VECTOR (0 to 7)
         );
end DEM_PACK;
    
architecture DEM_PACK_arch of DEM_PACK is
signal X :std_logic_vector (0 to 3);
begin
    DEMUL4 (DIN,S(2 downto 1),X);
    DEMUL2 (X(0),S(0),Y(0 to 1));
    DEMUL2 (X(1),S(0),Y(2 to 3));
    DEMUL2 (X(2),S(0),Y(4 to 5));
    DEMUL2 (X(3),S(0),Y(6 to 7)); 
end DEM_PACK_arch;