for_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 34 行

--******************************
--*   4 Bit Full Adder (FOR)   *
--*      Filename : FOR_1      *
--******************************

library IEEE;
use IEEE.std_logic_1164.all;

entity FOR_1 is
    port (
          A:  in STD_LOGIC_VECTOR (3 downto 0);
          B:  in STD_LOGIC_VECTOR (3 downto 0);
          C0: in STD_LOGIC;
          S:  out STD_LOGIC_VECTOR (3 downto 0);
          C4: out STD_LOGIC
         );
end FOR_1;

architecture FOR_1_arch of FOR_1 is

begin
process (A,B,C0)
variable Carry :std_logic;
begin
    Carry := C0; 
    for i in 0 to 3 loop
        S(i) <= A(i) xor B(i) xor Carry;
        Carry := (A(i) and B(i) ) or (A(i) and Carry) or (Carry and B(i));
    end loop;
    C4 <= Carry;
end process; 
       
end FOR_1_arch;