mealy_2.vhd

VHDL子程序集,包括各种例程资料以及源码.

--***********************************
--*  Detect "0101" Then Output '1'  *
--*         Filename : MEALY_2      *
--***********************************
        
library IEEE;
use IEEE.std_logic_1164.all;

entity MEALY_2 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          X:     in STD_LOGIC;
          Z:     out STD_LOGIC
         );
end MEALY_2;

architecture MEALY_2_arch of MEALY_2 is
type State is (S3,S2,S1,S0);
signal Present_State: State;
signal Next_State: State;
begin
process (CLK,RESET)

begin
    if RESET ='1' then 
       Present_State <= S0;
    elsif  CLK'event and CLK = '1' then
       Present_State <= Next_State;
    end if;
end process;  

process (X,Present_State)

begin
    case Present_State is
         when S0 =>
            if X ='0' then
               Next_State <= S1;
               Z <= '0';
            else
               Next_State <= S0;
               Z <= '0';
            end if;
         when S1 =>
            if X ='0' then
               Next_State <= S1;
               Z <= '0';
            else
               Next_State <= S2;
               Z <= '0';
            end if;
         when S2 =>
            if X ='0' then
               Next_State <= S3;
               Z <= '0';
            else
               Next_State <= S0;
               Z <= '0';
            end if;
         when S3 =>
            if X ='0' then
               Next_State <= S1;
               Z <= '0';
            else
               Next_State <= S2;
               Z <= '1';
            end if;            
    end case;
end process;

end MEALY_2_arch;