mul2_1_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 24 行

--**************************************
--*  2 To 1 Multiplexer Using Boolean  *
--*    Algebra With no Simplication    *
--*         Filename : MUL2_1_1        *
--**************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_1 is
    port (
        S: in STD_LOGIC_VECTOR (2 downto 0);
        F: out STD_LOGIC
    );
end MUL2_1_1;

architecture MUL2_1_1_arch of MUL2_1_1 is
begin
      F <= ((not S(2) and S(1) and not S(0)) or
           (not S(2) and  S(1) and S(0))) or
           ((S(2) and not S(1) and S(0)) or
           (S(2) and S(1) and S(0)));
end MUL2_1_1_arch;