moore_3.vhd

VHDL子程序集,包括各种例程资料以及源码.

--******************************
--*   Parity Checker After At  *
--*   Least Two Consective 0   *
--*     Filename : MOORE_3     *
--******************************
        
library IEEE;
use IEEE.std_logic_1164.all;

entity MOORE_3 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          X:     in STD_LOGIC;
          Z:     out STD_LOGIC
         );
end MOORE_3;

architecture MOORE_3_arch of MOORE_3 is
type State is (S5,S4,S3,S2,S1,S0);
signal Present_State: State;
signal Next_State: State;
begin
process (CLK,RESET)

begin
     if RESET ='1' then 
        Present_State <= S0;
     elsif  CLK'event and CLK = '1' then
        Present_State <= Next_State;
     end if;
end process;  

process (X,Present_State)

begin
    case Present_State is
         when S0 =>
            if X ='0' then
               Next_State <= S2;
            else
               Next_State <= S1;
            end if;
            Z <= '0';
         when S1 =>
            if X ='0' then
               Next_State <= S5;
            else
               Next_State <= S0;
            end if;
            Z <= '0';
         when S2 =>
            if X ='0' then
               Next_State <= S3;
            else
               Next_State <= S1;
            end if;
            Z <= '0';
         when S3 =>
            if X ='0' then
               Next_State <= S3;
            else
               Next_State <= S4;
            end if;
            Z <= '0';     
         when S4 =>
            if X ='0' then
               Next_State <= S4;
            else
               Next_State <= S3;
            end if;
            Z <= '1';
         when S5 =>
            if X ='0' then
               Next_State <= S4;
            else
               Next_State <= S0;
            end if;
            Z <= '0';
    end case;
end process;

end MOORE_3_arch;