block_3.vhd

VHDL子程序集,包括各种例程资料以及源码.

--********************************************
--*      1 To 8 Demultiplexer (BLOCK)        *
--*  One 1 To 4 DEMUL And Four 1 To 2 DEMUL  *
--*           Filename : BLOCK_3             *
--********************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity BLOCK_3 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (2 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 7)
         );
end BLOCK_3;

architecture BLOCK_3_arch of BLOCK_3 is
signal X:std_logic_vector(0 to 3);
begin

DEMUL4:BLOCK

begin
    X(0) <= DIN when S(2 downto 1) = "00" else '1';
    X(1) <= DIN when S(2 downto 1) = "01" else '1';
    X(2) <= DIN when S(2 downto 1) = "10" else '1';
    X(3) <= DIN when S(2 downto 1) = "11" else '1';
end BLOCK DEMUL4;

DEMUL2_1:BLOCK

begin
    Y(0) <= X(0) when S(0) = '0' else '1';
    Y(1) <= X(0) when S(0) = '1' else '1';
end BLOCK DEMUL2_1;

DEMUL2_2:BLOCK

begin
    Y(2) <= X(1) when S(0) = '0' else '1';
    Y(3) <= X(1) when S(0) = '1' else '1';
end BLOCK DEMUL2_2;

DEMUL2_3:BLOCK

begin
    Y(4) <= X(2) when S(0) = '0' else '1';
    Y(5) <= X(2) when S(0) = '1' else '1';
end BLOCK DEMUL2_3;

DEMUL2_4:BLOCK

begin
    Y(6) <= X(3) when S(0) = '0' else '1';
    Y(7) <= X(3) when S(0) = '1' else '1';
end BLOCK DEMUL2_4;

end BLOCK_3_arch;