fadder_c.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 55 行

--***********************************
--*  1 Bit Full Adder (CASE .. IS)  *
--*      Filename : FADDER_C        *
--***********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity FADDER_C is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          C0: in STD_LOGIC;
          S0: out STD_LOGIC;
          C1: out STD_LOGIC
          );
end FADDER_C;

architecture FADDER_C_arch of FADDER_C is
signal S: STD_LOGIC_VECTOR (2 downto 0);
begin
    S <= X0 & Y0 & C0;
process (S)

begin
    case S is 
       when "000"  =>
            S0 <= '0';
            C1 <= '0';
       when "001"  =>
            S0 <= '1';
            C1 <= '0';
       when "010"  =>
            S0 <= '1';
            C1 <= '0';           
       when "011"  =>
            S0 <= '0';
            C1 <= '1';
       when "100"  =>
            S0 <= '1';
            C1 <= '0';
       when "101"  =>
            S0 <= '0';
            C1 <= '1';
       when "110"  =>
            S0 <= '0';
            C1 <= '1'; 
       when others =>
            S0 <= '1';
            C1 <= '1';        
    end case;  
end process; 
         
end FADDER_C_arch;