mul4_1_s.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--***************************************
--* 4 TO 1 Multiplexer (WITH .. SELECT) *
--*         Filename : MUL4_1_S         *
--***************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL4_1_S is
    port (
          I: in STD_LOGIC_VECTOR (0 to 3);
          S: in STD_LOGIC_VECTOR (1 downto 0);
          Y: out STD_LOGIC
         );
end MUL4_1_S;

architecture MUL4_1_S_arch of MUL4_1_S is

begin
    with S select
       Y<= I(0) when "00",
           I(1) when "01",
           I(2) when "10",
           I(3) when others;  
end MUL4_1_S_arch;