srllo8.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 44 行

--*******************************
--*   8 Bit Shift Right Left    *
--*    AND LOADABLE Register    *
--*      Filename : SRLLO8      *
--*******************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity SRLLO8 is
    port (
          CLK:   in STD_LOGIC;
          DINS:  in STD_LOGIC;
          RESET: in STD_LOGIC;
          LOAD : in STD_LOGIC;
          MODE : in STD_LOGIC;
          DINP : in STD_LOGIC_VECTOR(7 downto 0);
          Q:     inout STD_LOGIC_VECTOR (7 downto 0)
         );
end SRLLO8;

architecture SRLLO8_arch of SRLLO8 is

begin
process (CLK,RESET)

begin   
    if RESET = '0' then 
       Q <= "00000000";
    elsif CLK'event and CLK = '1' then
       if LOAD = '1' then 
          Q <= DINP;
       else    
          if MODE = '1' then   
             Q <= DINS & Q (7 downto 1);
          else
             Q <= Q (6 downto 0) & DINS;
          end if;  
       end if;
    end if;  
end process; 
       
end SRLLO8_arch;