wait2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 34 行

--*******************************
--*  D F/F With Synchronous     *
--*   Clear Using WAIT UNTIL    * 
--*       Filename : WAIT2      *
--*******************************

library IEEE;
use IEEE.std_logic_1164.all;

entity WAIT2 is
    port (
          D:     in STD_LOGIC;
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     out STD_LOGIC
         );
end WAIT2;

architecture WAIT2_arch of WAIT2 is
   
begin
process

begin
    wait until CLK'event and CLK = '0';
    if RESET = '0' then
       Q <= '0';
    else  
       Q <= D;
    end if;   
end process;

end WAIT2_arch;