sr8.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 32 行

--********************************
--*  8 Bit Shift Right Register  *
--*        Filename : SR8        *
--********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity SR8 is
    port (
          CLK:   in STD_LOGIC;
          DIN:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (7 downto 0)
         );
end SR8;

architecture SR8_arch of SR8 is

begin
process (CLK,RESET,Q)

begin   
    if RESET = '0' then 
       Q <= "00000000";
    elsif CLK'event and CLK = '1' then
       Q <= DIN & Q (7 downto 1);
    end if;
end process;  
      
end SR8_arch;