funct_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 43 行

--*************************************
--*   16 Bit Parity Even Generator    *
--*    (FUNCTION IN ARCHITECTURE)     *
--*  Two 8 Bit Parity Even Generator  *
--*        Filename : FUNCT_1         *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity funct_1 is
    port (
          I:      in BIT_VECTOR (0 to 15);
          Parity: out BIT
         );
end funct_1;

architecture funct_1_arch of funct_1 is

function even8 (
                I: bit_vector (0 to 7)
               ) return bit is
         variable PE: bit; 	 
begin
    PE := '0';
    for K in I'left to I'right loop
        PE := PE xor I(K);
    end loop;
    return PE;
end even8;	    		  		 

signal High_byte : bit_vector (0 to 7); 
signal Low_byte  : bit_vector (0 to 7);
signal High : bit; 
signal Low  : bit;
begin
    High_byte <= I (8 to 15);
    Low_byte  <= I (0 to 7);
    High      <= even8 (High_byte);
    Low       <= even8 (Low_byte);
    Parity    <= High xor Low;	  
end funct_1_arch;