mul2_1_c.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 31 行

--*******************************************
--*  2 To 1 Multiplexer 2 Bit (CASE .. IS)  *
--*           Filename : MUL2_1_C           *
--*******************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_C is
    port (
          A: in STD_LOGIC_VECTOR (0 to 1);
          B: in STD_LOGIC_VECTOR (0 to 1);
          S: in Bit;
          Y: out STD_LOGIC_VECTOR (0 to 1)
         );
end MUL2_1_C;

architecture MUL2_1_C_arch of MUL2_1_C is

begin
process (S,A,B)

begin
    case S is
       when '0'    => Y <= A;
       when others => Y <= B;
    end case;   
end process;
	    
end MUL2_1_C_arch;