up_count.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 36 行

--***************************
--*    BCD  UP Counter      *
--*   Filename : UP_COUNT   *
--***************************
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity UP_COUNT is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (0 to 3)
         );
end UP_COUNT;

architecture UP_COUNT_arch of UP_COUNT is

begin
process (CLK,Q,RESET)

begin
    if (RESET = '1') then
       Q <= "0000";
    elsif CLK'event and CLK = '1' then
       if (Q = 9) then 
          Q <= "0000";
       else
          Q <= Q + 1;   
       end if;      
    end if;
end process;
         
end UP_COUNT_arch;