c1357.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*******************************
--*      Counter 1,3,5,7        *
--*      Filename : C1357       *
--*******************************

library IEEE;
use IEEE.std_logic_1164.all;

entity C1357 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (2 downto 0)
         );
end C1357;

architecture C1357_arch of C1357 is

begin
process (CLK,RESET,Q)

begin
    if RESET = '1' then 
       Q <= "001";
    elsif CLK'event and CLK = '1' then
       case Q is
          when "001"  => Q <= "011";
          when "011"  => Q <= "101";
          when "101"  => Q <= "111";
          when "111"  => Q <= "001";
          when others => Q <= "001";
       end case;
    end if;
end process;

end C1357_arch;