~~hier~~.tmp

VHDL子程序集,包括各种例程资料以及源码.

#BLOCK \ \ \ 0
#SIG C6/C10/N2 0
#SIG C6/C3/N0 0
#SIG C6/C3/N2 0
#SIG C6/C4/N2 0
#SIG C6/C5/N2 0
#SIG C6/C6/N2 0
#SIG C6/C7/N2 0
#SIG C6/C8/N2 0
#SIG C6/C9/N2 0
#SIG C6/N0 0
#SIG C6/N12 0
#SIG C6/N15 0
#SIG C6/N18 0
#SIG C6/N21 0
#SIG C6/N3 0
#SIG C6/N6 0
#SIG C6/N9 0
#SIG CLK 0
#SIG CLK_BUFGPed 0
#SIG N55 0
#SIG N56 0
#SIG N57 0
#SIG N58 0
#SIG N59 0
#SIG N60 0
#SIG N61 0
#SIG N62 0
#SIG N_Q7 1
#SIG N_Q6 1
#SIG N_Q5 1
#SIG N_Q4 1
#SIG N_Q3 1
#SIG N_Q2 1
#SIG N_Q1 1
#SIG N_Q0 1
#SIG N_RESET 0
#SIG Q7 2
#SIG Q6 2
#SIG Q5 2
#SIG Q4 2
#SIG Q3 2
#SIG Q2 2
#SIG Q1 2
#SIG Q0 2
#SIG RESET 0
#SIG SimGlobalReset 0
#COMP 0 C37 BUFGP
#PORT I i 0
#PORT O o 0
#COMP 0 C38 VCC
#PORT VCC o 0
#COMP 0 C39 GND
#PORT GROUND o 0
#COMP 0 C6/C10/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C10/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C3/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C3/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C3/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C4/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C4/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C4/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C5/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C5/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C5/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C6/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C6/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C6/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C7/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C7/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C7/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C8/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C8/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C8/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C6/C9/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C6/C9/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C6/C9/C3 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C_Q<0> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<1> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<2> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<3> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<4> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<5> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<6> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<7> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_RESET IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 Q_reg<0> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<1> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<2> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<3> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<4> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<5> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<6> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<7> FDC
#PORT D i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0