counter8.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 32 行

--***************************
--*     8 Bit UP Counter    *
--*   Filename : counter8   *
--***************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity counter8 is
    port (
          CLK:   in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (0 to 7);
          RESET: in STD_LOGIC
         );
end counter8;

architecture counter8_arch of counter8 is

begin
process (CLK,RESET,Q)

begin
     if RESET = '1' then
        Q <= "00000000";
     elsif CLK'event and CLK = '1' then
        Q <= Q + 1;
     end if;
end process;

end counter8_arch;