dff_clr.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 34 行

--***************************************
--*  D F/F With Synchronous  CLEAR    
--*         Filename : DFF_CLR        
--***************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DFF_CLR is
    port (
          D:     in STD_LOGIC;
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     out STD_LOGIC
         );
end DFF_CLR;

architecture DFF_CLR_arch of DFF_CLR is
   
begin
process (CLK,RESET)

begin
    if CLK'event and CLK = '0' then
       if RESET = '0' then
          Q <= '0';
       else
          Q <= D;
       end if;   
    end if;
end process;

end DFF_CLR_arch;