decod2_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 24 行

--*************************************
--*  2 To 4 Decoder (WHEN ... ELSE)   *
--*        Filename :DECOD2_4         *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DECOD2_4 is
    port (
          A: in STD_LOGIC_VECTOR (1 downto 0);
          Y: out STD_LOGIC_VECTOR (3 downto 0)
         );
end DECOD2_4;

architecture DECOD2_4_arch of DECOD2_4 is

begin
    Y(0) <='0' when  A = "00" else '1';
    Y(1) <='0' when  A = "01" else '1';
    Y(2) <='0' when  A = "10" else '1';
    Y(3) <='0' when  A = "11" else '1';
end DECOD2_4_arch;