mul2_1_2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--******************************************
--*  2 To 1 Multiplexer Using Truth Table  *
--*     Description  (WHEN ..... ELSE)     *
--*          Filename : MUL2_1_2           *
--******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_2 is
    port (
          S: in STD_LOGIC_VECTOR (2 downto 0);
          F: out STD_LOGIC
         );
end MUL2_1_2;

architecture MUL2_1_2_arch of MUL2_1_2 is

begin
    F <= '1' when S = "010" else
         '1' when S = "011" else
         '1' when S = "101" else
         '1' when S = "111" else
         '0';
end MUL2_1_2_arch;