mul_pack.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 27 行

--*************************************
--*   8 To 1 Multiplexer (FUNCTION)   *
--* Two 4 To 1 MUL And One 2 To 1 MUL *
--*     Those Declare In PACK_FUN     *
--*        Filename : MUL_PACK        *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;
use work.pack_fun.all;

entity MUL_PACK is
    port (
          I: in STD_LOGIC_VECTOR (0 to 7);
          S: in STD_LOGIC_VECTOR (2 downto 0);
          Y: out STD_LOGIC
         ); 
end MUL_PACK;

architecture MUL_PACK_arch of MUL_PACK is
signal result: std_logic_vector(0 to 1);
begin  
    result(1) <= MUL4 (I(4 to 7),S(1 downto 0));
    result(0) <= MUL4 (I(0 to 3),S(1 downto 0));
    Y         <= MUL2 (result,S(2));
end MUL_PACK_arch;