block_2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 44 行

--************************************
--*   1 To 4 Demultiplexer (BLOCK)   *
--*    Three 1 To 2 Demultiplexer    *
--*        Filename : BLOCK_2        *
--************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity BLOCK_2 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (1 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 3)
         );
end BLOCK_2;

architecture BLOCK_2_arch of BLOCK_2 is
signal X:std_logic_vector(1 downto 0);
begin

DEMUL2_1:BLOCK

begin
    X(0) <= DIN when S(1) = '0' else '1';
    X(1) <= DIN when S(1) = '1' else '1';
end BLOCK DEMUL2_1;

DEMUL2_2:BLOCK

begin
    Y(0) <= X(0) when S(0) = '0' else '1';
    Y(1) <= X(0) when S(0) = '1' else '1';
end BLOCK DEMUL2_2;

DEMUL2_3:BLOCK

begin
    Y(2) <= X(1) when S(0) = '0' else '1';
    Y(3) <= X(1) when S(0) = '1' else '1';
end BLOCK DEMUL2_3;

end BLOCK_2_arch;