block_4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 47 行

--**********************************
--*    1 Bit Full Adder (BLOCK)    *
--*   Two HAdder And One OR Gate   *
--*      Filename : BLOCK_4        *
--**********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity BLOCK_4 is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          C0: in STD_LOGIC;
          C1: out STD_LOGIC;
          S0: out STD_LOGIC
         );
end BLOCK_4;

architecture BLOCK_4_arch of BLOCK_4 is
signal CT: std_logic;
signal ST: std_logic;
signal CA: std_logic;
begin

HAdder_1:BLOCK

begin
    CT <= X0 and Y0; 
    ST <= X0 xor Y0;
end BLOCK HAdder_1;

HAdder_2: BLOCK

begin
    CA <= ST and C0;
    S0 <= ST xor C0;
end BLOCK HAdder_2;

OR_GATE:BLOCK

begin
    C1 <= CA or CT;
end BLOCK OR_GATE;
     
end BLOCK_4_arch;