dffall.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 39 行

--***************************************
--*      D F/F With Enable and        
--*     Asynchronous Clear Preset     
--*        Filename : DFFALL          
--***************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DFFALL is
    port (
        D:      in STD_LOGIC;
        CLK:    in STD_LOGIC;
        RESET:  in STD_LOGIC;
        SET:    in STD_LOGIC;
        ENABLE: in STD_LOGIC;
        Q:      out STD_LOGIC
    );
end DFFALL;

architecture DFFALL_arch of DFFALL is

begin
process (CLK,RESET,SET,ENABLE)

begin
    if RESET = '1' then 
       Q <= '0';
    elsif SET = '1' then
       Q <= '1'; 
    elsif CLK'event and CLK = '1' then
          if ENABLE = '1' then
             Q <= D;
          end if;  
    end if;     
end process; 
 
end DFFALL_arch;