demul1_2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 23 行

--*******************************************
--*  1 To 2 Demultiplexer (WHEN .... ELSE)  *
--*           Filename : DEMUL1_2           *
--*******************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEMUL1_2 is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC;
          Y:   out STD_LOGIC_VECTOR (0 to 1)
         );
end DEMUL1_2;

architecture DEMUL1_2_arch of DEMUL1_2 is

begin
    Y(0) <= DIN when S = '0' else '1';
    Y(1) <= DIN when S = '1' else '1';
end DEMUL1_2_arch;