updwnlo4.vhd

VHDL子程序集,包括各种例程资料以及源码.

--********************************
--*  4 Bit UP DOWN LOAD Counter  *
--*     Filename : UPDWNLO4      *
--********************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity updwnlo4 is
    port (
          CLK:      in STD_LOGIC;
          CLEAR:    in STD_LOGIC;
          LOAD:     in STD_LOGIC;
          UP_DOWN : in STD_LOGIC;
          DIN:      in STD_LOGIC_VECTOR (3 downto 0); 
          Q:        inout STD_LOGIC_VECTOR (3 downto 0)
         );
end updwnlo4;

architecture updwnlo4_arch of updwnlo4 is

begin
process (CLK,CLEAR)
    
begin
    if CLEAR = '0' then
       Q <= "0000";
    elsif CLK'event and CLK = '1' then
       if LOAD ='1' then
          Q <= DIN;
       else
          if UP_DOWN = '1' THEN 
             Q <= Q + 1;
          else
             Q <= Q - 1;
          end if;  
       end if;
    end if;  
end process;

end updwnlo4_arch;