mealy_1.out

来自「VHDL子程序集,包括各种例程资料以及源码.」· OUT 代码 · 共 28 行

Reading in the Synopsys vhdl primitives.

Inferred memory devices in process 
	in routine MEALY_1 line 23 in file
         'C:/book/mealy_1/mealy_1/mealy_1.vhd'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  Present_State_reg  | Flip-flop |   3   |  N  | N  | ?  | ?  | ?  | ?  | ?  |
===============================================================================

Present_State_reg<0>
--------------------
    Async-reset: RESET


Present_State_reg<2>
--------------------
    Async-set: RESET


Present_State_reg<1>
--------------------
    Async-reset: RESET


Writing to hnl file 'c:\BOOK\mealy_1\mealy_1\mealy_1/workdirs/WORK/MEALY_1.hnl'