sl4.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 32 行

--*******************************
--*  4 Bit Shift Left Register  *
--*       Filename : SL4        *
--*******************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity SL4 is
    port (
          CLK:   in STD_LOGIC;
          DIN:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout STD_LOGIC_VECTOR (0 to 3)
         );
end SL4;

architecture SL4_arch of SL4 is

begin
process (CLK,RESET,Q)

begin   
     if RESET = '0' then 
        Q <= "0000";
     elsif CLK'event and CLK = '1' then
        Q <= Q (1 to 3) & DIN;
     end if;
end process; 
       
end SL4_arch;