pack_com.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 30 行

--**************************************
--*  PACKAGE DECLARATION (COMPONENT)   *
--* Component :Half Adder And OR_Gate  *
--*       Filename : PACK_COM          *
--**************************************
 
library IEEE;
use IEEE.std_logic_1164.all;

PACKAGE PACK_COM  IS

component HA_COM
  port(
       X0: in STD_LOGIC;
       Y0: in STD_LOGIC;
       S0: out STD_LOGIC; 
       C1: out STD_LOGIC
      );
end component; 

component OR_GATE
  port (
        A: in STD_LOGIC;
        B: in STD_LOGIC;
        F: out STD_LOGIC
       );
end component;
                      
end PACK_COM;