or_gate.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 22 行

--********************************
--* Component Of 2 Input OR Gate *
--*      Filename : OR_GATE      *
--********************************

library IEEE;
use IEEE.std_logic_1164.all;

entity OR_GATE is
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          F: out STD_LOGIC
         );
end OR_GATE;

architecture OR_GATE_arch of OR_GATE is

begin
    F <= A or B;  
end OR_GATE_arch;