fa_pack.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 31 行

--************************************
--*   1 Bit Full Adder (Component)   *
--*  Two Half Adder And One OR_GATE  *
--*     Those Declare In PACK_COM    *
--*       Filename : FA_PACK         *
--************************************
 
library IEEE;
use IEEE.std_logic_1164.all;
use work.pack_com.all;

entity FA_PACK is
    port (
          X0: in STD_LOGIC;
          Y0: in STD_LOGIC;
          C0: in STD_LOGIC;
          S0: out STD_LOGIC;
          C1: out STD_LOGIC
         );
end FA_PACK;

architecture FA_PACK_arch of FA_PACK is
signal CT: STD_LOGIC;
signal ST: STD_LOGIC;
signal CA: STD_LOGIC;
begin
element1:HA_COM  port map (X0,Y0,ST,CT);
element2:HA_COM  port map (ST,C0,S0,CA);
element3:OR_GATE port map (CA,CT,C1);      
end FA_PACK_arch;