mul2_1_3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 21 行

--***************************************
--*  2 To 1 Multiplexer (WHEN .. ELSE)  *
--*         Filename : MUL2_1_3         *
--***************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_3 is
    port (
          S: in STD_LOGIC_VECTOR(2 downto 0);
          Y: out STD_LOGIC
         );
end MUL2_1_3;

architecture MUL2_1_3_arch of MUL2_1_3 is

begin
    Y<= S(1) when S(2)= '0' else S(0);
end MUL2_1_3_arch;