gener_5.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 35 行

--***********************************
--*   5 Bit  Counter (GENERIC)      *
--*   Using Component : COUN_COM    *
--*       Filename : GENER_5        *
--***********************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity GENER_5 is
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout integer range 0 to 31
         );
end GENER_5;

architecture GENER_5_arch of GENER_5 is

component COUN_COM
       generic (COUNT: integer);
       port (
            CLK:   in STD_LOGIC;
            RESET: in STD_LOGIC;
            Q:     inout integer range 0 to COUNT
           );
end component;         

begin
COUNTER: COUN_COM 
         generic map (31)
         port map (CLK,RESET,Q);
end GENER_5_arch;