coun_com.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*****************************************
--*    Counter Component (GENERIC)       *
--*       Filename : COUN_COM            *
--*****************************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity COUN_COM is
    generic (COUNT: integer := 3);
    port (
          CLK:   in STD_LOGIC;
          RESET: in STD_LOGIC;
          Q:     inout integer range 0 to COUNT
         );
end COUN_COM;

architecture COUN_COM_arch of COUN_COM is

begin
process (CLK,RESET)
 
begin
    if RESET = '1' then
       Q <= 0;
    elsif CLK'event and CLK = '1' then
       Q <= Q + 1;
       if Q = COUNT then
          Q <= 0;
       end if;
    end if;
end process;

end COUN_COM_arch;