mul2_1_f.vhd

VHDL子程序集,包括各种例程资料以及源码.

--**************************************
--*  2 To 1 Multiplexer (IF .. ELSE)   *
--*        Filename : MUL2_1_F         *
--**************************************
   
library IEEE;
use IEEE.std_logic_1164.all;

entity MUL2_1_F is
    port (
          I: in STD_LOGIC_VECTOR (1 downto 0);
          S: in STD_LOGIC;
          F: out STD_LOGIC 
         );
end MUL2_1_F;

architecture MUL2_1_F_arch of MUL2_1_F is

begin
process (S,I)

begin
    if S = '0' then 
       F <= I(0);
    else 
       F <= I(1);
    end if;
end process;
	
end MUL2_1_F_arch;