dem1_4_c.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 31 行

--*************************************
--* 1 To 4 Demultiplexer (CASE .. IS  *
--*       Filename : DEM1_4_C         *
--*************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEM1_4_C is
    port (
          DIN: in STD_LOGIC;
          S:   in STD_LOGIC_VECTOR (1 downto 0);
          Y:   out STD_LOGIC_VECTOR (0 to 3)
         );
end DEM1_4_C;

architecture DEM1_4_C_arch of DEM1_4_C is
begin
process (S,DIN)

begin
    case S is
       when "00"   => Y <= DIN & "111";
       when "01"   => Y <= '1' & DIN & "11";
       when "10"   => Y <= "11" & DIN & "1";
       when others => Y <= "111" & DIN;
    end case;
end process; 
  
end DEM1_4_C_arch;