for_2.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 30 行

--********************************
--*  8 Bit Parity ODD Generator  *
--*       Filename : FOR_2       *
--********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity FOR_2 is
    port (
          I:  in STD_LOGIC_VECTOR (0 to 7);
          PO: out STD_LOGIC
         );
end FOR_2;

architecture FOR_2_arch of FOR_2 is

begin
process (I)
variable PT:std_logic;
begin 
    PT := '1';
    for k in i'range loop
        PT := PT xor I(k);
    end loop;
    PO <= PT;
end process; 
    
end FOR_2_arch;