alias1.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*****************************************
--*   SN74138 3 TO 8 Decoder Simulation   *
--*          Filename : ALIAS1            *
--*****************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity alias1 is
    port (
          A: in STD_LOGIC_VECTOR (5 downto 0);
          Y: out STD_LOGIC_VECTOR (0 to 7)
         );
end alias1;

architecture alias1_arch of alias1 is
alias Sel:std_logic_vector (2 downto 0) is A (2 downto 0);
alias Enable:std_logic_vector (1 downto 0) is A (4 downto 3);
alias G:std_logic is A(5);	
begin
    Y(0) <= G when (Enable = "01" and Sel = "000") else '1';
    Y(1) <= G when (Enable = "01" and Sel = "001") else '1';
    Y(2) <= G when (Enable = "01" and Sel = "010") else '1';
    Y(3) <= G when (Enable = "01" and Sel = "011") else '1';
    Y(4) <= G when (Enable = "01" and Sel = "100") else '1';
    Y(5) <= G when (Enable = "01" and Sel = "101") else '1';
    Y(6) <= G when (Enable = "01" and Sel = "110") else '1';
    Y(7) <= G when (Enable = "01" and Sel = "111") else '1';
end alias1_arch;