gener_3.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 32 行

--**************************************
--* 16 Bit Binary To Gray Code Convert *
--*   (GENERIC) Component : BINTOGRA   *
--*         Filename : GENER_3         * 
--**************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity GENER_3 is
    port (
          B: in STD_LOGIC_VECTOR (0 to 15);
          G: out STD_LOGIC_VECTOR (0 to 15)
         );
end GENER_3;

architecture GENER_3_arch of GENER_3 is

component BINTOGRA 
      generic (number: integer range 0 to 31);
      port (
            B: in  STD_LOGIC_VECTOR (0 to number -1);
            G: out STD_LOGIC_VECTOR (0 to number -1)
           );
end component;
    
begin
Convert: BINTOGRA 
         generic map (16)
         port map (B,G);
end GENER_3_arch;