seven_s.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 33 行

--***********************************
--*  BCD To Seven Segnment Display  *
--*    Decoder ( WITH .. SELECT)    *
--*       Filename : SEVEN_S        *
--***********************************
 
library IEEE;
use IEEE.std_logic_1164.all;

entity SEVEN_S is
    port (
          S: in STD_LOGIC_VECTOR (3 downto 0);
          Y: out STD_LOGIC_VECTOR (6 downto 0)
         );
end SEVEN_S;

architecture SEVEN_S_arch of SEVEN_S is

begin
    with S select
       Y <= "1000000" when "0000",
            "1111001" when "0001",
            "0100100" when "0010",
            "0110000" when "0011",
            "0011001" when "0100",
            "0010010" when "0101",
            "0000010" when "0110",
            "1111000" when "0111",
            "0000000" when "1000",
            "0010000" when "1001",
            "1111111" when others;
end SEVEN_S_arch;