~~hier~~.tmp

VHDL子程序集,包括各种例程资料以及源码.

#BLOCK \ \ \ 0
#SIG C0/N12 0
#SIG C0/N18 0
#SIG C0/N24 0
#SIG C0/N30 0
#SIG C0/N36 0
#SIG C0/N42 0
#SIG C0/N48 0
#SIG C0/N6 0
#SIG C1/N6 0
#SIG C40/C2/N2 0
#SIG C40/C3/N2 0
#SIG C40/C4/N2 0
#SIG C40/C5/N2 0
#SIG C40/C6/N2 0
#SIG C40/C7/N2 0
#SIG C40/C8/N2 0
#SIG C40/C9/N2 0
#SIG C40/N12 0
#SIG C40/N15 0
#SIG C40/N18 0
#SIG C40/N21 0
#SIG C40/N3 0
#SIG C40/N6 0
#SIG C40/N9 0
#SIG CLEAR 0
#SIG CLK 0
#SIG CLK_BUFGPed 0
#SIG DIN7 1
#SIG DIN6 1
#SIG DIN5 1
#SIG DIN4 1
#SIG DIN3 1
#SIG DIN2 1
#SIG DIN1 1
#SIG DIN0 1
#SIG ENABLE 0
#SIG LOAD 0
#SIG N147 0
#SIG N148 0
#SIG N149 0
#SIG N150 0
#SIG N151 0
#SIG N152 0
#SIG N153 0
#SIG N154 0
#SIG N222 0
#SIG N_CLEAR 0
#SIG N_DIN7 2
#SIG N_DIN6 2
#SIG N_DIN5 2
#SIG N_DIN4 2
#SIG N_DIN3 2
#SIG N_DIN2 2
#SIG N_DIN1 2
#SIG N_DIN0 2
#SIG N_ENABLE 0
#SIG N_LOAD 0
#SIG N_Q7 3
#SIG N_Q6 3
#SIG N_Q5 3
#SIG N_Q4 3
#SIG N_Q3 3
#SIG N_Q2 3
#SIG N_Q1 3
#SIG N_Q0 3
#SIG N_UP_DOWN 0
#SIG Q7 4
#SIG Q6 4
#SIG Q5 4
#SIG Q4 4
#SIG Q3 4
#SIG Q2 4
#SIG Q1 4
#SIG Q0 4
#SIG UP_DOWN 0
#SIG SimGlobalReset 0
#COMP 0 C131 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C132 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C133 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C134 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C135 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C136 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C137 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C138 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C139 LUT1
#PORT I0 i 0
#PORT O o 0
#COMP 0 C140 LUT3
#PORT I0 i 0
#PORT I1 i 0
#PORT I2 i 0
#PORT O o 0
#COMP 0 C141 BUFGP
#PORT I i 0
#PORT O o 0
#COMP 0 C40/C2/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C2/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C2/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C3/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C3/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C3/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C4/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C4/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C4/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C5/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C5/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C5/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C6/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C6/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C6/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C7/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C7/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C7/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C8/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C8/C1 MUXCY_L
#PORT DI i 0
#PORT CI i 0
#PORT S i 0
#PORT LO o 0
#COMP 0 C40/C8/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C40/C9/C0 XORCY
#PORT CI i 0
#PORT LI i 0
#PORT O o 0
#COMP 0 C40/C9/C2 LUT2
#PORT I0 i 0
#PORT I1 i 0
#PORT O o 0
#COMP 0 C_CLEAR IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<0> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<1> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<2> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<3> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<4> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<5> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<6> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_DIN<7> IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_ENABLE IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_LOAD IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<0> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<1> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<2> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<3> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<4> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<5> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<6> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_Q<7> OBUF_S_12
#PORT I i 0
#PORT O o 0
#COMP 0 C_UP_DOWN IBUF
#PORT I i 0
#PORT O o 0
#COMP 0 Q_reg<0> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<1> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<2> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<3> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<4> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<5> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<6> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0
#COMP 0 Q_reg<7> FDCE
#PORT D i 0
#PORT CE i 0
#PORT C i 0
#PORT CLR i 0
#PORT Q o 0