updnloen.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 46 行

--*************************************
--* 8 Bit UP DOWN LOAD ENABLE Counter *
--*       Filename : UPDNLOEN         *
--*************************************
    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity updnloen is
    port (
          CLK:      in STD_LOGIC;
          CLEAR:    in STD_LOGIC;
          ENABLE:   in STD_LOGIC; 
          LOAD:     in STD_LOGIC;
          UP_DOWN : in STD_LOGIC;
          DIN:      in STD_LOGIC_VECTOR (7 downto 0); 
          Q:        inout STD_LOGIC_VECTOR (7 downto 0)
         );
end updnloen;

architecture updnloen_arch of updnloen is

begin
process (CLK,CLEAR)
    
begin
    if CLEAR = '0' then
       Q <= "00000000";
    elsif CLK'event and CLK = '1' then
       if LOAD ='1' then
          Q <= DIN;
       else
          if ENABLE = '1' then   
             if UP_DOWN = '1' THEN 
	        Q <= Q + 1;
             else
	        Q <= Q - 1;
             end if;  
          end if;
       end if;  
    end if;  
end process;

end updnloen_arch;