exnor_f.vhd

VHDL子程序集,包括各种例程资料以及源码.

--************************************
--*  EXNOR GATE (IF ..THEN .. ELSE)  *
--*        Filename : EXNOR_F        *
--************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity EXNOR_F is
    port (
          A: in STD_LOGIC;
          B: in STD_LOGIC;
          F: out STD_LOGIC
         );
end EXNOR_F;

architecture EXNOR_F_arch of EXNOR_F is
signal S: STD_LOGIC_VECTOR (1 downto 0);
begin
    S <= A & B;
process (S)

begin
    if S ="00" then  
       F <= '1';
    elsif S = "01" then     
       F <= '0';
    elsif S = "10" then
       F <= '0';
    else
       F <= '1';
    end if;
end process;
                
end EXNOR_F_arch;