mul4_1.vhd

来自「VHDL子程序集,包括各种例程资料以及源码.」· VHDL 代码 · 共 26 行

--*************************************
--* 4 To 1 Multiplexer(WHEN ... ELSE) *
--*         Filename : MUL4_1         *
--*************************************
     
library IEEE;
use IEEE.std_logic_1164.all;

entity MUL4_1 is
    port (
          I: in STD_LOGIC_VECTOR (0 to 3);
          S: in BIT_VECTOR (1 downto 0);
          Y: out STD_LOGIC
         );
end MUL4_1;

architecture MUL4_1_arch of MUL4_1 is

begin
    Y <= I(0) when  S = "00" else
         I(1) when  S = "01" else
         I(2) when  S = "10" else
         I(3) ;
end MUL4_1_arch;