dec2_4_s.vhd

VHDL子程序集,包括各种例程资料以及源码.

--*************************************
--*  2 To 4 Decoder (WITH .. SELECT)  *
--*        Filename : DEC2_4_S        *
--************************************

library IEEE;
use IEEE.std_logic_1164.all;

entity DEC2_4_S is
    port (
          A: in STD_LOGIC_VECTOR (1 downto 0);
          Y: out STD_LOGIC_VECTOR (0 to 3)
         );
end DEC2_4_S; 

architecture DEC2_4_S_arch of DEC2_4_S is

begin
    with A select
       Y <= "0111" when "00",
            "1011" when "01",
            "1101" when "10",
            "1110" when "11",
            "1111" when others;
end DEC2_4_S_arch;